Gaussian Noise Generation for Monte Carlo Simulations in Hardware

Hardware simulation offers the potential of improving execution speed by orders of magnitude over workstationor PC-based simulation. We describe a hardware Gaussian noise generator based on the Wallace method used as a key component in a hardware simulation system. The output of the noise generator accurately models a true Gaussian Probability Density Function (PDF) even at very high σ values. Its properties are explored using: (a) several different statistical tests, including the chi-square test and the Anderson-Darling test, and (b) an application for decoding of Low-Density Parity-Check (LDPC) codes. An implementation at 155MHz on a Xilinx Virtex-II XC2V4000-6 Field-Programmable Gate Array (FPGA) takes up 3% of the device and produces 155 million samples per second, which is eight times faster than a 2.6GHz Pentium-IV PC. The performance can be improved by exploiting parallelism: an XC2V4000-6 FPGA with 16 parallel instances of the noise generator at 115MHz can run 98 times faster than a 2.6GHz Pentium-IV PC. THE availability of high quality Gaussian random numbers is critical to many simulation, graphics and Monte Carlo applications. The work described here was originally motivated by ongoing advances in communications relating to channel codes [8], and in particular by the development of new generations of channel codes that operate on very long (thousands to tens of thousands of bits each) blocks of data. For these codes, it is often desirable to perform simulations of extremely large numbers of blocks in order to assess the bit error rate (BER) performance at rates as low as 10−12. The majority of simulations are performed using systems based on microprocessors, DSPs, or other softwareprogrammable devices. In these systems, the trigonometric, exponential, and other functions involved in many of the methods for obtaining Gaussian random variables can be performed using software libraries. Because of the emphasis on software-based simulation, far less attention has been focused on efficient hardware methods for implementation of Gaussian noise generators. However, well-optimized hardware implementations can routinely operate one or more orders of magnitude faster than similarly optimized software implementations. This gives a strong motivation to reexamine the issue of Gaussian noise generation in view of algorithms that map well into hardware implementations. There are many other applications in which very large simulations using Gaussian noise are valuable as well. These include financial modelling [11], simulation of economic systems and molecular dynamics simulations. Dong-U Lee is with the Department of Computing, Imperial College, London, United Kingdom (e-mail: [email protected] URL: http://www.ee.ucla.edu/ ̃dongu). The principal contribution of our work is a hardware Gaussian noise generator based on the Wallace method [10] that offers quality suitable for simulations involving very large numbers of noise samples. The noise generator occupies approximately 3% of the resources on a Xilinx Virtex-II XC2V4000-6 device, while producing over 155 million samples per second. The key contributions of our work include: • a hardware architecture for the Wallace method; • exploration of hardware implementations of the proposed architecture targeting advanced high-speed FPGAs; • evaluation of the proposed approach using several different statistical tests, including the chi-square test and the Anderson-Darling test, as well as through application to a large communications simulation involving Low-Density Parity-Check (LDPC) channel codes [2], [6].